Embedded control systems often incorporate “on-chip” clock generation and a certain precision and stability of such a clock is required depending on the application. Typically, generation of a clock signal may be achieved using a so called “RC oscillator” or “relaxation oscillator” where the output toggles when a capacitor is charged to a certain threshold. One known RC oscillator circuit is described in US 20100237955 A1. A similar circuit arrangement is illustrated in FIG. 1. Referring to FIG. 1, an oscillator circuit 100 is arranged to provide an output clock signal CLK having a particular frequency. The oscillator circuit 100 comprises a voltage reference Vref, a first current source 101, a first capacitor 102, a first capacitor switch 103, a second current source 104, a second capacitor 105, a second capacitor switch 106, a first comparator 107, a second comparator 108 and a flip-flop 109. The voltage reference Vref is provided from a reference current source 110 and a reference RC circuit 111 in a commonly known manner. The first capacitor 102 is arranged to, by operation of the first capacitor switch 103, be chargeable by the first current source 101 to a first capacitor voltage on a first capacitor node 112 in a first half-phase of the output clock cycle and to be dischargeable in a second half-phase of the output clock cycle. The second capacitor 105 is arranged to, by operation of the second capacitor switch 106, be chargeable by the second current source 104 to a second capacitor voltage on a second capacitor node 113 in the second half-phase of the output clock cycle and to be dischargeable in a first half-phase of the output clock cycle. The first comparator 107 is arranged to provide a first comparator output from continuously comparing the first capacitor voltage to the reference voltage. The second comparator 108 is arranged to provide a second comparator output from continuously comparing the second capacitor voltage to the reference voltage. The flip-flop 109 is connected to both comparators and generates the output clock signal CLK and an inverted output clock signal on its outputs. The flip-flop's CLK output and its inverted output operate the first and second switches respectively. The oscillator frequency can be trimmed to the target frequency by the choice of resistor in the RC circuit 111. Such conventional embedded oscillator circuits can suffer from output frequency long term drift caused by drift in the offset of the comparator(s). While initial frequency offsets may be compensated to some extent by factory trim, the resulting drift may not be low enough to meet certain specifications which may force a system designer to use external oscillators such as a quartz crystal oscillator. Offset is mostly caused by transistor threshold mismatch. The threshold can change over time due to mobile hydrogen (moving in and out the channel region), NBTI (negative bias instability especially on pmos devices), HCl (hot carrier injection) and other effects. Matching transistors can have an initial offset caused by lithography difference or well proximity effects, for example. This causes unwanted clock frequency instability with temperature. Drift effects may be more pronounced on devices with relatively thin oxide layers and it is not possible to trim the drift effects away because they are mostly unforeseeable in direction and magnitude. Furthermore, since the overall magnitude of long-term drift can only be predicted, a guaranteed tolerance in a device's specification is difficult to achieve.